/*
 * Copyright (c) 2021-2023 HPMicro
 *
 * SPDX-License-Identifier: BSD-3-Clause
 *
 */


#ifndef HPM_MIPI_CSI_PHY_H
#define HPM_MIPI_CSI_PHY_H

typedef struct {
    __RW uint32_t SOFT_RST;                    /* 0x0: soft reset control */
    __RW uint32_t PHY_RCAL;                    /* 0x4: dphy resistor calibration */
    __RW uint32_t ULP_RX_EN;                   /* 0x8: enable lprx and ulprx */
    __R  uint32_t VOFFCAL_OUT;                 /* 0xC: hs-rx dc-offset auto-calibration results */
    __RW uint32_t CSI_CTL01;                   /* 0x10: dphy hardcore control */
    __RW uint32_t CSI_CTL23;                   /* 0x14: dphy hardcore control */
    __R  uint8_t  RESERVED0[4];                /* 0x18 - 0x1B: Reserved */
    __RW uint32_t CSI_VINIT;                   /* 0x1C: ulp lp-rx input threshold voltage trimming for data lane */
    __RW uint32_t CLANE_PARA;                  /* 0x20: clock lane parameter */
    __RW uint32_t T_HS_TERMEN;                 /* 0x24: t-termen of all datalane */
    __RW uint32_t T_HS_SETTLE;                 /* 0x28: t-settle of all data lanes */
    __R  uint8_t  RESERVED1[4];                /* 0x2C - 0x2F: Reserved */
    __RW uint32_t T_CLANE_INIT;                /* 0x30: t-init of clock lane */
    __RW uint32_t T_LANE_INIT0;                /* 0x34: t-init of data lane0 */
    __RW uint32_t T_LANE_INIT1;                /* 0x38: t-init of data lane1 */
    __R  uint8_t  RESERVED2[8];                /* 0x3C - 0x43: Reserved */
    __RW uint32_t TLPX_CTRL;                   /* 0x44: the time of tlpx_ctrl of all lane */
    __RW uint32_t NE_SWAP;                     /* 0x48: lane swap and dp/dn swap select */
    __RW uint32_t MISC_INFO;                   /* 0x4C: misc info of dphyrx_pcs control */
    __R  uint8_t  RESERVED3[32];               /* 0x50 - 0x6F: Reserved */
    __RW uint32_t BIST_TEST0;                  /* 0x70: bist test control */
    __RW uint32_t BIST_TEST1;                  /* 0x74: bist test control */
    __RW uint32_t BIST_TEST2;                  /* 0x78: bist test control */
    __R  uint32_t BIST_TEST3;                  /* 0x7C: bist test control */
    __R  uint8_t  RESERVED4[32];               /* 0x80 - 0x9F: Reserved */
    __RW uint32_t BURN_IN_TEST0;               /* 0xA0: burn-in test control */
    __RW uint32_t BURN_IN_TEST1;               /* 0xA4: burn-in test control */
    __R  uint32_t BURN_IN_TEST2;               /* 0xA8: bist test control */
    __R  uint8_t  RESERVED5[4];                /* 0xAC - 0xAF: Reserved */
    __R  uint32_t BURN_IN_TEST4;               /* 0xB0: bist test control */
    __R  uint32_t BURN_IN_TEST5;               /* 0xB4: burn-in test control */
    __R  uint32_t BURN_IN_TEST6;               /* 0xB8: burn-in test control */
    __R  uint8_t  RESERVED6[8];                /* 0xBC - 0xC3: Reserved */
    __R  uint32_t BURN_IN_TEST9;               /* 0xC4: burn-in test control */
    __R  uint8_t  RESERVED7[8];                /* 0xC8 - 0xCF: Reserved */
    __RW uint32_t DEBUG_INFO;                  /* 0xD0: debug data control */
    __RW uint32_t DEBUG_CFG_REG0;              /* 0xD4: the hardcore interface control in debug mode */
    __RW uint32_t DEBUG_CFG_REG1;              /* 0xD8: the hardcore interface control in debug mode */
    __R  uint8_t  RESERVED8[3126];             /* 0xDC - 0xD11: Reserved */
    __RW uint32_t DEBUG_CFG_REG2;              /* 0xD12: the hardcore interface control in debug mode */
    __RW uint32_t DEBUG_CFG_REG3;              /* 0xD16: the hardcore interface control in debug mode */
    __R  uint8_t  RESERVED9[6];                /* 0xD1A - 0xD1F: Reserved */
    __RW uint32_t DEBUG_CFG_REG4;              /* 0xD20: the hardcore interface control in debug mode */
    __RW uint32_t DEBUG_CFG_REG5;              /* 0xD24: the hardcore interface control in debug mode */
} MIPI_CSI_PHY_Type;


/* Bitfield definition for register: SOFT_RST */
/*
 * HS_CLK_SOFT_RST (RW)
 *
 * the soft reset of clk_hs domain
 */
#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK (0x2U)
#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT (1U)
#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT) & MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK)
#define MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_MASK) >> MIPI_CSI_PHY_SOFT_RST_HS_CLK_SOFT_RST_SHIFT)

/*
 * CFG_CLK_SOFT_RST (RW)
 *
 * the soft reset of clk_cfg domain
 */
#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK (0x1U)
#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT (0U)
#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT) & MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK)
#define MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_MASK) >> MIPI_CSI_PHY_SOFT_RST_CFG_CLK_SOFT_RST_SHIFT)

/* Bitfield definition for register: PHY_RCAL */
/*
 * RCAL_DONE (RO)
 *
 * hs-rx terminal trimming done indicator signal
 */
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_MASK (0x20000UL)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_SHIFT (17U)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_DONE_SHIFT)

/*
 * RCAL_OUT (RO)
 *
 * hs-rx terminal trimming results
 */
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_MASK (0x1E000UL)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_SHIFT (13U)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_OUT_SHIFT)

/*
 * RCAL_CTL (RW)
 *
 * rcal function control
 */
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK (0x1FE0U)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT (5U)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_CTL_SHIFT)

/*
 * RCAL_TRIM (RW)
 *
 * default value of HS-RX terminal configure
 */
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK (0x1EU)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT (1U)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_TRIM_SHIFT)

/*
 * RCAL_EN (RW)
 *
 * enable hs-rx terminal trimming
 */
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK (0x1U)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT (0U)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT) & MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK)
#define MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_MASK) >> MIPI_CSI_PHY_PHY_RCAL_RCAL_EN_SHIFT)

/* Bitfield definition for register: ULP_RX_EN */
/*
 * CSI_1_ULPRX_EN (RW)
 *
 * data lane1 ulp-rx receiver enable control
 */
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK (0x80U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT (7U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_1_ULPRX_EN_SHIFT)

/*
 * CSI_0_ULPRX_EN (RW)
 *
 * data lane0 ulp-rx receiver enable control
 */
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK (0x40U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT (6U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_0_ULPRX_EN_SHIFT)

/*
 * CSI_CLK_ULPRX_EN (RW)
 *
 * clock lane ulp-rx receiver enable control
 */
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK (0x20U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT (5U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_ULPRX_EN_SHIFT)

/*
 * CSI_1_LPRX_EN (RW)
 *
 * data lane1 lp-rx receiver enable control
 */
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK (0x2U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT (1U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_1_LPRX_EN_SHIFT)

/*
 * CSI_CLK_LPRX_EN (RW)
 *
 * clock lane lp=rx receiver enable control
 */
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK (0x1U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT (0U)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK)
#define MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_MASK) >> MIPI_CSI_PHY_ULP_RX_EN_CSI_CLK_LPRX_EN_SHIFT)

/* Bitfield definition for register: VOFFCAL_OUT */
/*
 * CSI_CLK_VOFFCAL_DONE (RO)
 *
 * clock lane hs-rx dc-offset auto-calibration done
 */
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_MASK (0x20000000UL)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_SHIFT (29U)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_DONE_SHIFT)

/*
 * CSI_CLK_VOFFCAL_OUT (RO)
 *
 * clock lane hs-rx dc-offset auto-calibration results
 */
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_MASK (0x1F000000UL)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_SHIFT (24U)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_CLK_VOFFCAL_OUT_SHIFT)

/*
 * CSI_0_VOFFCAL_DONE (RO)
 *
 * data lane0 hs-rx dc-offset auto-calibration done
 */
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_MASK (0x800000UL)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_SHIFT (23U)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_0_VOFFCAL_DONE_SHIFT)

/*
 * CSI_O_VOFFCAL_OUT (RO)
 *
 * data lane0 hs-rx dc-offset auto-calibration result
 */
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_MASK (0x7C0000UL)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_SHIFT (18U)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_O_VOFFCAL_OUT_SHIFT)

/*
 * CSI_1_VOFFCAL_DONE (RO)
 *
 * data lane1 hs-rx dc-offset auto-calibration done
 */
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_MASK (0x20000UL)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_SHIFT (17U)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_DONE_SHIFT)

/*
 * CSI_1_VOFFCAL_OUT (RO)
 *
 * data lane1 hs-rx dc-offset auto-calibration result
 */
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_MASK (0x1F000UL)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_SHIFT (12U)
#define MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_MASK) >> MIPI_CSI_PHY_VOFFCAL_OUT_CSI_1_VOFFCAL_OUT_SHIFT)

/* Bitfield definition for register: CSI_CTL01 */
/*
 * CSI_CTL1_7 (RW)
 *
 * clock lane hs-rx dc-offset auto-calibration enable
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK (0x20000000UL)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT (29U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_7_SHIFT)

/*
 * CSI_CTL1_6 (RW)
 *
 * clock lane hs-rx dc-offset trimming control
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK (0x1F000000UL)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT (24U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_6_SHIFT)

/*
 * CSI_CTL1_5 (RW)
 *
 * ulprx_vref_trim
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK (0x600000UL)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT (21U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_5_SHIFT)

/*
 * CSI_CTL1_4 (RW)
 *
 * bypass hs_rx_voffcal_en
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK (0x100000UL)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT (20U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_4_SHIFT)

/*
 * CSI_CTL1_3 (RW)
 *
 * hs_rx_voffcal_trim_polar
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK (0x80000UL)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT (19U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_3_SHIFT)

/*
 * CSI_CTL1_2 (RW)
 *
 * ulprx_lpen
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK (0x40000UL)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT (18U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_2_SHIFT)

/*
 * CSI_CTL1_1 (RW)
 *
 * force data lane-n and clock lane lp/ulprx to be normal operation
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK (0x20000UL)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT (17U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_1_SHIFT)

/*
 * CSI_CTL1_0 (RW)
 *
 * force data lane-n and clock lane hs-rx to be normal operation
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK (0x10000UL)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT (16U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL1_0_SHIFT)

/*
 * CSI_CTL0_7 (RW)
 *
 * clock lane hs-rx dc-offset auto-calibration enable
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK (0x2000U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT (13U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_7_SHIFT)

/*
 * CSI_CTL0_6 (RW)
 *
 * clock lane hs-rx dc-offset trimming control
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK (0x1F00U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT (8U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_6_SHIFT)

/*
 * CSI_CTL0_5 (RW)
 *
 * ulprx_vref_trim
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK (0x60U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT (5U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_5_SHIFT)

/*
 * CSI_CTL0_4 (RW)
 *
 * bypass hs_rx_voffcal_en
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK (0x10U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT (4U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_4_SHIFT)

/*
 * CSI_CTL0_3 (RW)
 *
 * hs_rx_voffcal_trim_polar
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK (0x8U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT (3U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_3_SHIFT)

/*
 * CSI_CTL0_2 (RW)
 *
 * ulprx_lpen
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK (0x4U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT (2U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_2_SHIFT)

/*
 * CSI_CTL0_1 (RW)
 *
 * force data lane-n and clock lane lp/ulprx to be normal operation
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK (0x2U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT (1U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_1_SHIFT)

/*
 * CSI_CTL0_0 (RW)
 *
 * force data lane-n and clock lane hs-rx to be normal operation
 */
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK (0x1U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT (0U)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK)
#define MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_MASK) >> MIPI_CSI_PHY_CSI_CTL01_CSI_CTL0_0_SHIFT)

/* Bitfield definition for register: CSI_CTL23 */
/*
 * CSI_CTL3_3 (RW)
 *
 * data lane-1 skew trimming enable
 */
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK (0x10000000UL)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT (28U)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_3_SHIFT)

/*
 * CSI_CTL3_2 (RW)
 *
 * data lane-1 hs-rx skew adjust with binary code
 */
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK (0xF000000UL)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT (24U)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_2_SHIFT)

/*
 * CSI_CTL3_1 (RW)
 *
 * data lane-0 skew trimming enable
 */
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK (0x100000UL)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT (20U)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_1_SHIFT)

/*
 * CSI_CTL3_0 (RW)
 *
 * data lane-0 hs-rx skew adjust with binary code
 */
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK (0xF0000UL)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT (16U)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK)
#define MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_MASK) >> MIPI_CSI_PHY_CSI_CTL23_CSI_CTL3_0_SHIFT)

/* Bitfield definition for register: CSI_VINIT */
/*
 * CSI_LPRX_VREF_TRIM (RW)
 *
 * pt ft indicator in csi clk data lane
 */
#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK (0xF00000UL)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT (20U)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT) & MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_LPRX_VREF_TRIM_SHIFT)

/*
 * CSI_CLK_LPRX_VINT (RO)
 *
 * pt ft indicator in csi clk lane
 */
#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_MASK (0xF0000UL)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_SHIFT (16U)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_CLK_LPRX_VINT_SHIFT)

/*
 * CSI_1_LPRX_VINIT (RO)
 *
 * pt ft indicator in csi lane-1
 */
#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_MASK (0xF0U)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_SHIFT (4U)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_1_LPRX_VINIT_SHIFT)

/*
 * CSI_0_LPRX_VINIT (RO)
 *
 * pt ft indicator in csi lane-0
 */
#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_MASK (0xFU)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_SHIFT (0U)
#define MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_MASK) >> MIPI_CSI_PHY_CSI_VINIT_CSI_0_LPRX_VINIT_SHIFT)

/* Bitfield definition for register: CLANE_PARA */
/*
 * T_CLK_TERMEN (RW)
 *
 * time for the clock lane receiver to enable the HS line termination
 */
#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK (0xFF00U)
#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT (8U)
#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK)
#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_MASK) >> MIPI_CSI_PHY_CLANE_PARA_T_CLK_TERMEN_SHIFT)

/*
 * T_CLK_SETTLE (RW)
 *
 * the value of tclk-settle of clklane
 */
#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK (0xFFU)
#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT (0U)
#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK)
#define MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_MASK) >> MIPI_CSI_PHY_CLANE_PARA_T_CLK_SETTLE_SHIFT)

/* Bitfield definition for register: T_HS_TERMEN */
/*
 * T_D1_TERMEN (RW)
 *
 * the value of ths-termen of datalane1
 */
#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK (0xFF00U)
#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT (8U)
#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT) & MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK)
#define MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_MASK) >> MIPI_CSI_PHY_T_HS_TERMEN_T_D1_TERMEN_SHIFT)

/*
 * T_D0_TERMEN (RW)
 *
 * the value of ths-termen of datalane0
 */
#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK (0xFFU)
#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT (0U)
#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT) & MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK)
#define MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_MASK) >> MIPI_CSI_PHY_T_HS_TERMEN_T_D0_TERMEN_SHIFT)

/* Bitfield definition for register: T_HS_SETTLE */
/*
 * T_D1_SETTLE (RW)
 *
 * the value of ths-settle of data lane1
 */
#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK (0xFF00U)
#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT (8U)
#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT) & MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK)
#define MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_MASK) >> MIPI_CSI_PHY_T_HS_SETTLE_T_D1_SETTLE_SHIFT)

/*
 * T_D0_SETTLE (RW)
 *
 * the value of ths-settle of data lane0
 */
#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK (0xFFU)
#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT (0U)
#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT) & MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK)
#define MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_MASK) >> MIPI_CSI_PHY_T_HS_SETTLE_T_D0_SETTLE_SHIFT)

/* Bitfield definition for register: T_CLANE_INIT */
/*
 * T_CLK_INIT (RW)
 *
 * initialization time of lock lane
 */
#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK (0xFFFFFFUL)
#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT (0U)
#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT) & MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK)
#define MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_MASK) >> MIPI_CSI_PHY_T_CLANE_INIT_T_CLK_INIT_SHIFT)

/* Bitfield definition for register: T_LANE_INIT0 */
/*
 * T_D0_INIT (RW)
 *
 * initialization time of data lane
 */
#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK (0xFFFFFFUL)
#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT (0U)
#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT) & MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK)
#define MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_MASK) >> MIPI_CSI_PHY_T_LANE_INIT0_T_D0_INIT_SHIFT)

/* Bitfield definition for register: T_LANE_INIT1 */
/*
 * T_D1_INIT (RW)
 *
 * initialization time of data lane
 */
#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK (0xFFFFFFUL)
#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT (0U)
#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT) & MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK)
#define MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_MASK) >> MIPI_CSI_PHY_T_LANE_INIT1_T_D1_INIT_SHIFT)

/* Bitfield definition for register: TLPX_CTRL */
/*
 * EN_TLPX_CHECK (RW)
 *
 * enable the tlpx width check
 */
#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK (0x100U)
#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT (8U)
#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT) & MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK)
#define MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_MASK) >> MIPI_CSI_PHY_TLPX_CTRL_EN_TLPX_CHECK_SHIFT)

/*
 * TLPX (RW)
 *
 * the width of tlpx
 */
#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK (0xFFU)
#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT (0U)
#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT) & MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK)
#define MIPI_CSI_PHY_TLPX_CTRL_TLPX_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_TLPX_CTRL_TLPX_MASK) >> MIPI_CSI_PHY_TLPX_CTRL_TLPX_SHIFT)

/* Bitfield definition for register: NE_SWAP */
/*
 * DPDN_SWAP_LANE1 (RW)
 *
 * datalane1 dpdn swap
 */
#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK (0x200U)
#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT (9U)
#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK)
#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_MASK) >> MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LANE1_SHIFT)

/*
 * DPDN_SWAP_LAN0 (RW)
 *
 * datalane0 dpdn swap
 */
#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK (0x100U)
#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT (8U)
#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK)
#define MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_MASK) >> MIPI_CSI_PHY_NE_SWAP_DPDN_SWAP_LAN0_SHIFT)

/*
 * LANE_SWAP_LAN1 (RW)
 *
 * data lane1 swap
 */
#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK (0xCU)
#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT (2U)
#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK)
#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_MASK) >> MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LAN1_SHIFT)

/*
 * LANE_SWAP_LANE0 (RW)
 *
 * data lane0 swap
 */
#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK (0x3U)
#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT (0U)
#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK)
#define MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_MASK) >> MIPI_CSI_PHY_NE_SWAP_LANE_SWAP_LANE0_SHIFT)

/* Bitfield definition for register: MISC_INFO */
/*
 * ULPS_LP10_SEL (RW)
 *
 * the lp10 select signal in ulps_exit state
 */
#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK (0x2U)
#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT (1U)
#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT) & MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK)
#define MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_MASK) >> MIPI_CSI_PHY_MISC_INFO_ULPS_LP10_SEL_SHIFT)

/*
 * LONG_SOTSYNC_EN (RW)
 *
 * at least six zero is checked before sot swquence "00011101"
 */
#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK (0x1U)
#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT (0U)
#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT) & MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK)
#define MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_MASK) >> MIPI_CSI_PHY_MISC_INFO_LONG_SOTSYNC_EN_SHIFT)

/* Bitfield definition for register: BIST_TEST0 */
/*
 * BIST_DONE_LAN1 (RO)
 *
 * bist_done of lane1
 */
#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_MASK (0x80U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_SHIFT (7U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN1_SHIFT)

/*
 * BIST_DONE_LAN0 (RO)
 *
 * bist_done of lane0
 */
#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_MASK (0x40U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_SHIFT (6U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_DONE_LAN0_SHIFT)

/*
 * BIST_OK_LANE1 (RO)
 *
 * bist_ok of lane1
 */
#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_MASK (0x8U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_SHIFT (3U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE1_SHIFT)

/*
 * BIST_OK_LANE0 (RO)
 *
 * bist_ok of lane0
 */
#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_MASK (0x4U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_SHIFT (2U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_OK_LANE0_SHIFT)

/*
 * BIST_EN_SEL (RW)
 *
 * the source of bist_en sel
 */
#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK (0x2U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT (1U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SEL_SHIFT)

/*
 * BIST_EN_SOFT (RW)
 *
 * enable prbs bist test
 */
#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK (0x1U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT (0U)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK)
#define MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_MASK) >> MIPI_CSI_PHY_BIST_TEST0_BIST_EN_SOFT_SHIFT)

/* Bitfield definition for register: BIST_TEST1 */
/*
 * PRBS_CHECK_NUM (RW)
 *
 * the byte num of prbs bist check num
 */
#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT (0U)
#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT) & MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK)
#define MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_MASK) >> MIPI_CSI_PHY_BIST_TEST1_PRBS_CHECK_NUM_SHIFT)

/* Bitfield definition for register: BIST_TEST2 */
/*
 * PRBS_SEED (RW)
 *
 * the seed of prbs7
 */
#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK (0xFF0000UL)
#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT (16U)
#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT) & MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK)
#define MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_MASK) >> MIPI_CSI_PHY_BIST_TEST2_PRBS_SEED_SHIFT)

/*
 * PRBS_ERR_THRESHOLD (RW)
 *
 * the threshold of prbs bist error
 */
#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK (0xFFFFU)
#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT (0U)
#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT) & MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK)
#define MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_MASK) >> MIPI_CSI_PHY_BIST_TEST2_PRBS_ERR_THRESHOLD_SHIFT)

/* Bitfield definition for register: BIST_TEST3 */
/*
 * PRBS_ERR_NUM_LAN1 (RO)
 *
 * the byte num of mismatch data of data lane1 in bist mode
 */
#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_MASK (0xFFFF0000UL)
#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_SHIFT (16U)
#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN1_SHIFT)

/*
 * PRBS_ERR_NUM_LAN0 (RO)
 *
 * the byte num of mismatch data of data lane0 in bist mode
 */
#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_MASK (0xFFFFU)
#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_SHIFT (0U)
#define MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BIST_TEST3_PRBS_ERR_NUM_LAN0_SHIFT)

/* Bitfield definition for register: BURN_IN_TEST0 */
/*
 * BURN_IN_OK_CLAN (RO)
 *
 * burn_in_ok of clock lane
 */
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_MASK (0x40U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_SHIFT (6U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_CLAN_SHIFT)

/*
 * BURN_IN_OK_LAN1 (RO)
 *
 * burn_in_ok of lane1
 */
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_MASK (0x8U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_SHIFT (3U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN1_SHIFT)

/*
 * BURN_IN_OK_LAN0 (RO)
 *
 * burn_in_ok of lane0
 */
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_MASK (0x4U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_SHIFT (2U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_OK_LAN0_SHIFT)

/*
 * BURN_IN_EN_SEL (RW)
 *
 * the source of prbs burn_in_en sel
 */
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK (0x2U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT (1U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SEL_SHIFT)

/*
 * BURN_IN_EN_SOFT (RW)
 *
 * enable prbs burn_in test
 */
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK (0x1U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT (0U)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK)
#define MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST0_BURN_IN_EN_SOFT_SHIFT)

/* Bitfield definition for register: BURN_IN_TEST1 */
/*
 * BURN_IN_SEED (RW)
 *
 * the seed of prbs7 for brun-in test
 */
#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK (0xFFU)
#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT (0U)
#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT) & MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK)
#define MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST1_BURN_IN_SEED_SHIFT)

/* Bitfield definition for register: BURN_IN_TEST2 */
/*
 * BURN_IN_ERR_NUM_LAN1 (RO)
 *
 * the bit num of mismatch data on data lan1 in burn-in mode
 */
#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_MASK (0xFFFF0000UL)
#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_SHIFT (16U)
#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN1_SHIFT)

/*
 * BURN_IN_ERR_NUM_LAN0 (RO)
 *
 * the bit num of mismatch data on data lan0 in burn-in mode
 */
#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_MASK (0xFFFFU)
#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_SHIFT (0U)
#define MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST2_BURN_IN_ERR_NUM_LAN0_SHIFT)

/* Bitfield definition for register: BURN_IN_TEST4 */
/*
 * BURN_IN_ERR_NUM_CLAN (RO)
 *
 * the bit num of mismatch data on clock lane in burn-in mode
 */
#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_MASK (0xFFFFU)
#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_SHIFT (0U)
#define MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST4_BURN_IN_ERR_NUM_CLAN_SHIFT)

/* Bitfield definition for register: BURN_IN_TEST5 */
/*
 * BURN_IN_CHECK_NUM_LAN0 (RO)
 *
 * the checked bit num of lane0
 */
#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_SHIFT (0U)
#define MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST5_BURN_IN_CHECK_NUM_LAN0_SHIFT)

/* Bitfield definition for register: BURN_IN_TEST6 */
/*
 * BURN_IN_CHECKED_NUM_LAN1 (RO)
 *
 * the checked bit num of lane1
 */
#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_SHIFT (0U)
#define MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST6_BURN_IN_CHECKED_NUM_LAN1_SHIFT)

/* Bitfield definition for register: BURN_IN_TEST9 */
/*
 * BURN_IN_CHECK_NUM_CLAN (RO)
 *
 * the checked bit num of clock lane
 */
#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_SHIFT (0U)
#define MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_MASK) >> MIPI_CSI_PHY_BURN_IN_TEST9_BURN_IN_CHECK_NUM_CLAN_SHIFT)

/* Bitfield definition for register: DEBUG_INFO */
/*
 * DEBUG_MODE_SEL (RW)
 *
 * the debug bus sel
 */
#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK (0x3F0000UL)
#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT (16U)
#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT) & MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK)
#define MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_MASK) >> MIPI_CSI_PHY_DEBUG_INFO_DEBUG_MODE_SEL_SHIFT)

/* Bitfield definition for register: DEBUG_CFG_REG0 */
/*
 * DEBUG_CFG_REG0 (RW)
 *
 * debug config register0
 */
#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT (0U)
#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK)
#define MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG0_DEBUG_CFG_REG0_SHIFT)

/* Bitfield definition for register: DEBUG_CFG_REG1 */
/*
 * DEBUG_CFG_REG1 (RW)
 *
 * debug config register1
 */
#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT (0U)
#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK)
#define MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG1_DEBUG_CFG_REG1_SHIFT)

/* Bitfield definition for register: DEBUG_CFG_REG2 */
/*
 * DEBUG_CFG_REG2 (RW)
 *
 * debug config register2
 */
#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT (0U)
#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK)
#define MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG2_DEBUG_CFG_REG2_SHIFT)

/* Bitfield definition for register: DEBUG_CFG_REG3 */
/*
 * DEBUG_CFG_REG3 (RW)
 *
 * debug config register3
 */
#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT (0U)
#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK)
#define MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG3_DEBUG_CFG_REG3_SHIFT)

/* Bitfield definition for register: DEBUG_CFG_REG4 */
/*
 * DEBUG_CFG_REG4 (RW)
 *
 * debug config register4
 */
#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT (0U)
#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK)
#define MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG4_DEBUG_CFG_REG4_SHIFT)

/* Bitfield definition for register: DEBUG_CFG_REG5 */
/*
 * DEBUG_CFG_REG5 (RW)
 *
 * debug config register5
 */
#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK (0xFFFFFFFFUL)
#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT (0U)
#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SET(x) (((uint32_t)(x) << MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT) & MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK)
#define MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_GET(x) (((uint32_t)(x) & MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_MASK) >> MIPI_CSI_PHY_DEBUG_CFG_REG5_DEBUG_CFG_REG5_SHIFT)




#endif /* HPM_MIPI_CSI_PHY_H */
